This application relies for priority upon Korean Patent Application No. 2000-60033, filed on Oct. 12, 2000, the contents of which are herein incorporated by reference in their entirety.
In a flash memory device, increased integration, improved operating efficiency or performance, and insurance of mass productivity are very important goals that should be continuously improved and developed. However, because of the complex elements incorporated into the flash memory device, it is not easy to simultaneously achieve these goals.
The complexity of the integrated elements results from the operating characteristics of the flash memory device. Namely, the flash memory device, a nonvolatile memory type, is designed to have three operating modesxe2x80x94programming, erasing, and reading data. In order to carry out these three modes, the flash memory device needs to form high and low voltage transistors in a peripheral circuit area thereof along with transistors having double gates in a cell area thereof. The gate insulating layer and source/drain regions in the high voltage transistor can be formed to have respectively different thickness and structure compared with those in the low voltage transistor. Also, the peripheral circuit area of the flash memory device generally has a complementary metal oxide silicon (CMOS) structure which, like that of other memory devices, simultaneously uses p-channel and n-channel transistors to increase efficiency or performance.
As element complexity increases, the processes required to manufacture a flash memory device also become more complicated and difficult. Among the characteristics of the flash memory device, the endurance characteristic showing whether or not thermal damage has occurred with repeated programming and erasing and the data retention characteristic showing how long it continues to store data after programming are both important. The endurance and data retention characteristics are dependent on the quality of a dielectric layer and a gate insulating layer which are in contact with floating gates in a cell area of the flash memory device. Also, the characteristics of high and low voltage transistors in a peripheral circuit area, which has a large influence on functional operation of the flash memory device, is dependent on the quality of the gate insulating layer. However, it is not easy to form both a superior gate insulating layer and quality dielectric layer.
FIG. 1 is a top plan view showing a portion of a cell area of a general NOR type flash memory.
Referring now to FIG. 1, isolation areas 11 are formed on a substrate to form an active region. The active region comprises a plurality of longitudinal band shaped sub-regions which are defined respectively by a plurality of longitudinal openings or gaps of the isolation areas 11. Floating gates 15 are disposed between word lines 13 and the active region on the portions of the substrate surfaces where the word lines 13 overlay the active region. The floating gates 15 are separated from the word lines 13 and the active region by a dielectric layer and a gate insulating layer, respectively. Also, each floating gate 15 partially overlaps an isolation area 11 at both of its edges. Source lines 17, positioned parallel to the word lines 13, are formed by removing portions of the isolation area 11 positioned on the surface of the substrate using the word lines 13 as a mask, and then carrying out ion implantation on the exposed surface of the substrate. Contacts 19, with which bit lines 21 are connected, are formed in a drain region between the word lines 13 disposed between the source lines 17.
FIG. 2 to FIG. 4 are cross-sectional views of a semiconductor device showing the sequential formation of layers used in a conventional method of manufacturing a NOR type flash memory device. In the drawings, the processes of depositing and etching materials to form transistors in a cell area and transistors in high and low voltage regions of a peripheral circuit area are illustrated step by step. The cell area is shown as a section taken along the direction of the word lines, and the peripheral circuit area is shown as a section taken along the direction of connecting source/drain regions without dividing p-channel and n-channel.
Referring now to FIG. 2, isolation area 11 are formed on a substrate 10 to define an active region. Then, a buffer oxide layer 12 is formed on the active region of the substrate 10. In order to form all sorts of impurity wells, various ion implantation processes are performed. Each process is composed of forming an ion implantation mask according to the region to be implanted, carrying out ion implantation operations and removing the ion implantation mask.
Referring to FIG. 3, the buffer oxide layer 12 (from FIG. 2) in a cell region is removed and then a tunneling gate insulating layer 121 is formed. Thereafter, a floating gate layer is deposited on the tunneling gate insulating layer 121 and patterned to form a floating gate layer pattern 131. Then, an oxide-nitride-oxide (ONO) dielectric layer 141 is formed over the whole surface of the substrate to cover the floating gate layer pattern 131. Thereafter, an etch mask 143 is formed of a photoresist to cover the cell region, and the dielectric layer 141, the floating gate layer 131, and the buffer oxide layer 12 covering the active region in the peripheral circuit area are removed, so that surface of the active region in the peripheral circuit area is exposed. Then, the etch mask 143 is removed.
In succession, ion implantation processes for controlling threshold voltages of the high and low voltage transistors are carried out.
Referring to FIG. 4, a gate insulating layer 222xe2x80x2 for the high voltage region is formed in the peripheral circuit area. Then, an etch mask, which exposes a low voltage region of the peripheral circuit area, is used to remove the portion of gate insulating layer 222xe2x80x2 covering the low voltage region. After removing the high voltage gate insulating layer 222xe2x80x2 formed in the low voltage region, the etch mask is removed and a gate insulating layer 223 is formed in the low voltage region. The gate insulating layers 222xe2x80x2, 223 are formed of a silicon oxide layer which is made of thermally oxidized silicon. A silicon oxide layer is used rather than a silicon oxide nitride layer, otherwise a silicon oxide layer of the ONO dielectric layer 141 in the cell area exposed after the etch mask 143 is removed can be nitrified, negatively influencing the permittivity.
Next, a control gate layer 151 is deposited over the whole surface of the substrate and patterned to form word lines. While forming word lines in the cell region, the dielectric layer 141 and the floating gate layer 131 in the rest of the cell regions not overlaid by word lines are also removed by etching. Source lines positioned parallel to the word lines are formed by removing portions of the isolation area 11 positioned between the word lines using an etch mask pattern and the word lines as a mask, and then carrying out ion implantation in the exposed surface of the substrate. At this time, ion implantation is also carried out against a drain region. Thereafter, gate electrodes 153 for high and low voltage transistors are formed by patterning the control gate layer 151.
In the conventional method of manufacturing flash memory devices explained above, the dielectric layer 141 is generally formed of an ONO layer. Also, in several process steps, photoresist patterns are formed as etch or ion implantation masks on the dielectric layer 141 and/or the surface of the substrate 10. In particular, after the dielectric layer is formed over the whole surface of the substrate, a patterning process which forms a photoresist pattern on the dielectric layer is carried out. Also, in order to carry out ion implantation processes for controlling threshold voltages of the high and low voltage transistors, photoresist patterns are formed on the dielectric layer in the cell and the exposed surface of the substrate in the peripheral circuit area after the etch mask for removing the dielectric layer and the floating gate layer in the peripheral circuit area is removed. Also, after the gate insulating layer 222xe2x80x2 for the high voltage region is formed in the peripheral circuit area, a photoresist pattern exposing the low voltage region in the peripheral circuit area is formed on the dielectric layer in the cell area and the gate insulating layer 222xe2x80x2 in the high voltage area to remove the gate insulating layer 222xe2x80x2 for high voltage from the low voltage region. Thus, in respective subsequent processes, the used photoresist patterns have to be removed.
Since the photoresist patterns are crystallized to the polymer shape during the ion implantation or etch process, in order to completely remove the photoresist patterns, a mixture of NH4OH, H2O2, and de-ionized water or a hydrofluoric acid should be used as the etchant. However, in this case, the ONO dielectric layer can be damaged by the etchant, negatively impacting the function of the flash memory device. Accordingly, the photoresist patterns are removed only by O2 plasma ashing and sulfuric acid (H2SO4) strip processes in the respective subsequent processes, so that it is impossible to completely remove the photoresist patterns. Remains of the photoresist patterns may act to accelerate degradation or aging of the dielectric layer or the gate insulating layer.
Also, even if the photoresist patterns are completely removed, a very small amount of heavy metal contained in the photoresist can still remain on the surface of the substrate or the ONO dielectric layer. The metal may diffuse in subsequent processes such as annealing or thermal oxidation, or cause crystal damage to occur on the substrate in the etching or ion implantation process, thereby deteriorating characteristics of the dielectric layer or the gate insulating layer and in turn functions of the resultant flash memory device.
The present invention relates to method of manufacturing a flash memory device, and more particularly to method of manufacturing a flash memory device that improves the quality of the gate insulating layer and the dielectric layer of the device. These improvements greatly improve the operating characteristics of the device.
It is an object of the present invention to provide an improved method of manufacturing a flash memory device which can improve the characteristics of the dielectric layer and the gate insulating layer.
It is another object of the present invention to provide an improved method of manufacturing a flash memory device which can minimize damage to the silicon substrate due to the ion implantation or etching process in order to reduce the shift and variation of the threshold voltage, and further to prevent functional defects due to the photoresist cleaning process from occurring.
These and other objects are provided, according to the present invention, by preventing photoresist patterns from being formed and removed directly on a surface of the substrate or the dielectric layer, and by separately forming a control gate layer of transistors in a cell area and a gate layer of transistors in a peripheral circuit area of the substrate. A preferred embodiment of the present invention includes the steps of forming a gate insulating layer in high and low voltage regions of a peripheral circuit area and then forming a gate layer on the gate insulating layer, followed by forming a transistor structure in a cell area of the substrate composed of a tunneling gate insulating layer, a floating gate layer, a dielectric layer and a control gate layer. Specifically, the step of forming the transistor structure in the cell area is carried out after the step of forming the gate insulating layer and the gate layer in the peripheral circuit area.
The thickness of the gate insulating layer can be varied according to regions on which it is disposed, i.e., high and low voltage regions of the peripheral circuit area. This step can be carried out by forming a gate insulating layer for high voltage in at least all the active regions of the peripheral circuit area, removing the gate insulating layer for high voltage from the low voltage region of the peripheral circuit area by using an etch mask, forming a gate insulating layer for low voltage on the low voltage region after removing the etch mask, and forming the gate layer over the substrate where the gate insulating layer for low voltage is formed.
The step of forming the transistor structure in the cell area can be carried out by the sub-steps comprising: forming the tunneling gate insulating layer in all the active regions of the cell area, forming a floating gate layer pattern over the tunneling gate insulating layer, forming the dielectric layer over the floating gate layer pattern, forming a control gate layer over the dielectric layer, and carrying out self-aligned etching against the dielectric layer and then the floating gate layer pattern by using word lines as an etch mask after forming the word lines by patterning the control gate layer.